Bitstream 질문입니다.

- 강의 내용외의 개인 질문은 받지 않아요 (개별 과제, 고민 상담 등..)
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안녕하세요. ZC702로 학습 중입니다.

implation까지는 다 잘됩니다..

하지만 1장에서 bitstream에서 막혔습니다.

board가 달라서 생기는 문제인 것 같습니다..

이럴 때는 어떻게 해야할까요..?

도와주시면 감사하겠습니다!

로그는 아래와 같습니다.

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.

This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity

or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards.

This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined.

To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].

NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command),

add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[2], and led[0].

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 12 logical ports have no user assigned specific location constraint (LOC).

This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage

to the device or the components to which it is connected. To correct this violation, specify all pin locations.

This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.

To allow bitstream creation with unspecified pin locations (not recommended), use this command:

set_property SEVERITY {Warning} [get_drc_checks UCIO-1].

NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command),

add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[2], and led[0].

WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.

INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings

INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.

ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

INFO: [Common 17-83] Releasing license: Implementation

17 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.

write_bitstream failed

ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.