Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T)

FPGA Design by someone with over 20 years of experience 📑

Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or want to improve their skills in the field.

However, Verilog and FPGA are very special fields, so it is very difficult to find a lecture that explains them in detail. FPGA manufacturers provide documentation, but there are so many documents in English that it is difficult to know which document to look at.

I have been working as a developer in the industry for over 20 years and currently run a one-man business. I created this course because I wanted to share the knowledge I have accumulated so far with people who are working as developers or preparing to become developers.

The course consists of a total of 5 lectures.

This lecture is the fifth lecture and is about LVDS (Serdes). LVDS is used for low-voltage, high-speed serial communication. FPGA supports Serdes to implement LVDS. Understand LVDS, create Serdes, and understand its operation through simulation. Finally, implement LVDS transmission and reception and verify its operation on the development board (HIL-A35T).

If there is anything you do not understand in the lecture, please post a question through the Infraon community or the cafe I run and I will answer it.

💾 Please check before taking the class!

• This lecture is a text lecture in electronic document format . All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.

• The tool used in this lecture is vivado 2018.3.

• The board used for the practical training of this lecture is HIL-A35T, which we developed for the lecture. You can purchase it from our company's smart store (Smart store link: https://smartstore.naver.com/ihil)

• Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.

Lecture Features ✨

Everything about LVDS communication

There are very few documents that cover implementing LVDS in FPGAs. In fact, Xilinx provides a lot of documents, but they are so numerous and in English that it is difficult to know which documents to look at.

This lecture covers everything about LVDS. It explains LVDS, creates Serdes, understands the operation through simulation, and downloads the result to the target board to implement LVDS transmission and reception. Through this process, you can understand everything about LVDS and use it in the field.

Upgrade your Verilog skills

For those who want to learn Verilog, LVDS is a very good skill. There are many people who have a lot of development experience but have not encountered LVDS. We provide an opportunity to upgrade Verilog to the next level.

Provides source code applicable to practical use.

For those who purchase this course, we will provide all the sources explained in the course. The sources provided are composed of materials that have been coded and verified from the beginning while producing the course. In addition, they are composed of codes that can be used immediately in the field. We hope that you will become a master of LVDS through this course.

📢 The course consists of a total of 5 lectures. This is the 5th lecture.

Lecture 1: Verilog FPGA Program 1

• Implementing basic functions

Lecture 2: Verilog FPGA Program 2

• Microblaze

Lecture 3: Verilog FPGA Program 3

• DDR Controller

Lecture 4: Verilog FPGA Program 4

• MCU Porting

Lecture 5: Verilog FPGA Program 5

• LVDS / Serdes

  
  

Basics (Appendix): Basics of FPGA Utilization Using Verilog

📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.

1. Arty A7-35T board

   
   

   • Verilog FPGA Program 1 (Arty A7-35T)

   • Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)

   • Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)

   • Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

   • Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)

2. Zynq mini 7020 board

   • Verilog FPGA Program 1 (Zynq mini 7020)

   • Verilog ZYNQ Program1 (Zynq mini 7020)

3. HIL-A35T board (developed in-house for lectures)

   • Verilog FPGA Program 1 (HIL-A35T)

   • Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)

     
     

   • Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

   • Verilog FPGA Program 4 (MCU Porting, HIL-A35T)

   • Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T)

Detailed Curriculum 📚

Section 1. HW Configuration

• Describes the development board (HIL-A35T).

Section 2. LVDS Review

• Understand the ins and outs of LVDS.

• Describes important information about Serdes (ISERDESE2, OSERDESE2).

Section 3. LVDS Implementation

• Create a Serdes IP and understand its operation through simulation.

• Implement LVDS transmission and reception code and verify it with simulation.

• Download the results to the target board and check the results.

Section 4. 2-Lane, 4-Lane Implementation

• Explain how to extend Lane and see the results on the board.

  
  

Section 5. Implementing maximum transfer rates

• Describes how to implement maximum transfer rates and verify the results on the board.