Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
Through this lecture, you will be able to implement a DDR Controller using FPGA.
This course is prepared for Intermediate Learners.
What you will learn!
DDR Controller
Frame Buffer
Verilog HDL
DDR Memory Controller implemented in FPGA 🛠️
FPGAs have many functions available in IP form.
Among them, we will explain the DDR Controller, which is mainly used to process image data.
FPGA Design by someone with over 20 years of experience 📑
Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or want to improve their skills in the field.
However, Verilog and FPGA are very special fields, so it is very difficult to find a lecture that explains them in detail. FPGA manufacturers provide documentation, but there are so many documents in English that it is difficult to know which document to look at.
I have been working as a developer in the industry for over 20 years and currently run a one-man business. I created this course because I wanted to share the knowledge I have accumulated so far with people who are working as developers or preparing to become developers.
The course consists of a total of 4 parts.
This lecture is the third lecture and covers DDR Controller for processing video data. To process video data, a Frame Buffer is required. DDR is fast and cheap, so it is widely used as a Frame Buffer.
This lecture implements a DDR Controller using MIG (Memory Interface Generator) provided by Xilinx. It also implements a Frame Buffer for image data processing. If you understand the contents of this lecture, you can implement any application that uses DDR.
If there is anything you do not understand in the lecture, please post a question through the Inflearn community or the cafe I run and I will answer it.
💾 Please check before taking the class!
This lecture is a text lecture in electronic document format . All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.
The tool used in this lecture is vivado 2018.3.
The board used for the practical training of this lecture is HIL-A35T, which we developed for the lecture. You can purchase it from our company's smart store (Smart Store Link: https://smartstore.naver.com/ihil)
Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.
Lecture Features ✨
Everything about DDR Controller
There are few documents that cover DDR Memory Controller. This lecture explains all the processes in detail. It explains all the processes from creating and simulating Memory IP to implementing DDR Memory Controller for general use and implementing Frame Buffer for image data processing. In addition, each source code is configured so that you can verify it through simulation and understand its operation.
Upgrade your Verilog skills
For those who want to learn Verilog, DDR Memory Controller is a very good skill. There are many people who have a lot of development experience but have not encountered DDR Memory Controller. We provide an opportunity to upgrade Verilog to the next level.
Provides source code applicable to practical use.
For those who purchase this course, we will provide all the sources explained in the course. The sources provided are composed of materials that have been coded and verified from the beginning while producing the course. In addition, they are composed of codes that can be used immediately in the field. We hope that you will become a master of DDR Controller through this course.
📢 The course consists of a total of 4 lectures. This is the 3rd lecture.
Lecture 1: Verilog FPGA Program 1
Implementing basic functions
Lecture 2: Verilog FPGA Program 2
Microblaze
Lecture 3: Verilog FPGA Program 3
DDR Controller
Lecture 4: Verilog FPGA Program 4
MCU Porting
Basics: Basics of FPGA Utilization Using Verilog
📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.
Arty A7-35T board
Verilog FPGA Program 1 (Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)
Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)
Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)
Zynq mini 7020 board
Verilog FPGA Program 1 (Zynq mini 7020)
Verilog ZYNQ Program1 (Zynq mini 7020)
HIL-A35T board (developed in-house for lectures)
Verilog FPGA Program 1 (HIL-A35T)
Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)
Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
Verilog FPGA Program 4 (MCU Porting, HIL-A35T)
Detailed Curriculum 📚
Section 1. HW Configuration
Section 2. Creating DDR Controller IP
Generate DDR Controller IP using MIG. DDR Controller has many options during the generation process. You need to know and set these options well to generate IP that works properly.
This lecture explains these processes in detail.
Section 3. Simulation
It is very important to understand the behavior of the generated IP.
Understand IP operation through simulation.
Section 4. Implementing User Interface Logic
Based on understanding the behavior through simulation, we implement User Interface Logic that can be used universally.
Implement DDR full-range write, read, and verification and check the results on the board.
Section 5. Improving DDR Memory Access Speed
Added in v2.4, implements a method to improve DDR Memory Access speed.
Section 6. Implementing the Frame Buffer
Implement a Frame Buffer that processes video data using User Interface Logic.
Section 7. Implementing the 32Bits Interface
Added in v2.5, it implements a 32-bit interface using two 16-bit DDR memories.
Section 8. Spartan6 DDR Controller Implementation
Implementing Spartan6 DDR Controller using ISE version 14.7.
Section 9. DDR4 Controller Implementation
Added in v2.7, implements DDR4 Controller.
Recommended for
these people!
Who is this course right for?
Image data processing using FPGA
Frame Buffer Implementation
If you want to learn Verilog
If you want to learn FPGA
Need to know before starting?
Verilog
alive
FPGA
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저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고
현재는 작은 기업의 대표로 있습니다.
주요 경력사항은
Verilog HDL을 이용한 FPGA 설계
CCTV용 ISP ASIC 개발 (약 10년)
OLED Display 검사장비 개발 (약 3년)
FPGA를 이용한 장비 개발
MCU FW
STM32
PIC32
AVR, ATMEGA
DSP (TI)
Windows Application Program
Visual Studio MFC, C++
입니다.
Curriculum
All
277 lectures
are provided.