Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)
Learn how to implement MicroBlaze on Xilinx FPGAs.
This course is prepared for Basic Learners.
What you will learn!
Using MicroBlaze on FPGAs
Verilog program
FPGA program
Using MicroBlaze on Xilinx FPGAs!
MicroBlaze is a processor provided in IP form in FPGA. MicroBlaze separates the Processor Core and Peripherals, allowing users to configure the Peripherals according to their purposes.
FPGA Design by someone with over 20 years of experience 📑
Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or want to improve their skills in the field.
However, Verilog and FPGA are very special fields, so it is very difficult to find a lecture that explains them in detail. FPGA manufacturers provide documentation, but there are so many documents in English that it is difficult to know which document to look at.
I have been working as a developer in the industry for over 20 years and currently run a one-man business. I created this course because I wanted to share the knowledge I have accumulated so far with people who are working as developers or preparing to become developers.
The lecture consists of a total of 4 parts.
This lecture is the second lecture and is about MicroBlaze. MicroBlaze is a 32bits MicroProcessor provided by Xilinx. Using MicroBlaze, you can implement the Processor and User Logic simultaneously in the FPGA. Also, if you implement the Interface between the Processor and User Logic, you can implement the SOC (system on chip) in the FPGA. This lecture is structured so that even beginners can easily follow along, including the installation and usage of tools, explanation of the code, simulating the code, and checking the results on the development board.
Becoming a capable developer is not an easy task. It requires a lot of effort. It is very good to have a friendly guide during that difficult process.
This course contains a lot of content. If you are not an experienced developer, it may be difficult to understand everything at once. You will be able to gradually make it your own by repeatedly coding, simulating, and checking the results on the board.
If you can fully understand and utilize the contents of this lecture, you can become a very good developer.
If there is anything you do not understand in the lecture, please post a question through the Infraon community or the cafe I run and I will answer it.
📢 Please make sure to check before taking the class!
This lecture is a text lecture in electronic document format. All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.
This lecture is based on Vitis 2022.1, the version after 2019.
The board used for the practical training of this lecture is HIL-A35T, which we developed for the lecture. You can purchase it from our smart store (Smart store link: https://smartstore.naver.com/ihil)
Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.
📢 The course consists of a total of 4 lectures. This is the 2nd lecture.
Lecture 1: Verilog FPGA Program 1
Implementing basic functions
Lecture 2: Verilog FPGA Program 2
Microblaze
Lecture 3: Verilog FPGA Program 3
DDR Controller
Lecture 4: Verilog FPGA Program 4
MCU Porting
Basics: Basics of FPGA Utilization Using Verilog
📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.
Arty A7-35T board (Digilent)
Verilog FPGA Program 1 (Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)
Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)
Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)
Zynq mini 7020 board
Verilog FPGA Program 1 (Zynq mini 7020)
Verilog ZYNQ Program1 (Zynq mini 7020)
HIL-A35T board (developed in-house for lectures)
Verilog FPGA Program 1 (HIL-A35T)
Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)
Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
Verilog FPGA Program 4 (MCU Porting, HIL-A35T)
Lecture Features ✨
The lecture content is
Immediately applicable to practice!
Tested and proven
Open source provided!
Debugging, development required
Windows app program provided!
Learn things like this 📚
Section 1. HW Configuration
Section 2. Vitis 2022.1 Installation Process
Vitis is a very heavy tool. I will explain what you need to be careful about when installing it and how to install it without conflicting with your current Vivado.
Section 3. Print “Hello world” to the screen with MicroBlaze
This section aims to give you an overview of the flow.
Section 4. Peripheral of MicoBlaze
We will explain the GPIO, Timer, Uart, and Interrupt that are mainly used. Since the peripherals provided by MicroBlaze are similar, if you learn the contents of the lecture, you can easily use other peripherals.
Section 5. Knowledge that can be applied in practice
Most of the material ends with dealing with the Peripheral. However, the purpose of using MicroBlaze in FPGA is to control the user-designed logic through MicroBlaze. Ultimately, it is to control the user-designed logic through the UI(User Interface).
In this lecture, we added 4 PWM modules to configure User Logic. We configured Register Map to control User Logic, and controlled User Logic through MicroBlaze and UI. We explained and implemented all of these processes and showed the results.
The content described in this section can be applied directly to practice. All you have to do is add User Logic and Register Map, and you can use all other processes as implemented.
Section 6. lwIP Echo Server
This is about implementing an Echo Server using lwIP. Implement a DDR Controller to use Cache (Instruction Cache, Data Cache) in MicroBlaze.
Section 7. Using lwIP
This explains the process of adding User Logic to TCP/IP communication using lwIP. This explains the process of sending a command using TCP/IP from a PC, receiving the command via lwIP, and controlling the LED of the board in User Logic. Through this, the interface between lwIP and User Logic is implemented and the results are confirmed.
Section 8. TCP/IP Implementation Using W5500 Module
This is the content added in v1.4. It is about implementing TCP/IP using wiznet's w5500 module. It implements data transmission and reception by connecting to a PC and a network. If you apply this, you will be able to apply it in various fields that utilize TCP/IP.
Section 9. Block Memory Interface - 1
Added in v1.5. Implements the Block Memory Interface provided by default in Block Design.
Section 10. Block Memory Interface - 2
This is what was added in v1.5. Block Memory is added to User Logic to implement Block Memory Interface. By applying this, User Register Map is implemented, and an example of controlling frequency and duty of PWM is implemented.
Section 11. Implementing the w5500 Interface
Implement TCP/IP communication using the w5500 module.
Recommended for
these people!
Who is this course right for?
Anyone interested in MicroBlaze
Anyone interested in FPGA
Anyone interested in Verilog
Need to know before starting?
C language
Verilog HDL
Xilinx FPGA
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저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고
현재는 작은 기업의 대표로 있습니다.
주요 경력사항은
Verilog HDL을 이용한 FPGA 설계
CCTV용 ISP ASIC 개발 (약 10년)
OLED Display 검사장비 개발 (약 3년)
FPGA를 이용한 장비 개발
MCU FW
STM32
PIC32
AVR, ATMEGA
DSP (TI)
Windows Application Program
Visual Studio MFC, C++
입니다.
Curriculum
All
358 lectures
are provided.