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Hardware

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Semiconductor

Verilog ZYNQ Program 1 (Zynq mini 7020)

This lecture is about using the Xilinx ZYNQ board. If you understand the contents of this lecture, you will learn the skills to understand Embedded_SW + User_Logic and apply them to practice.

73 students are taking this course

Verilog HDL
zynq
FPGA
vivado

This course is prepared for Intermediate Learners.

What you will learn!

  • Verilog coding

  • Utilizing ZYNQ Board

  • How to use Vivado, Vitis

  • PS area, PL area implementation

  • Embedded fw + User Logic

Into the new world of ZYNQ
Give it a try!

📢 Please note before taking the class.

  • This lecture is a text lecture in the form of an electronic document (PDF) of approximately 80,000 characters. All source files described in the lecture are provided to those who take the lecture. The lecture source code can be downloaded from Section 0 [Material Sharing Link].

Lecture Features ✨

#1.
I wanted to learn Zynq
For everyone.

There are almost no professional technical materials covering Zynq. Although Xilinx provides materials, there are so many documents that it is very difficult to know which documents to look at. This lecture explains in detail the basics of Zynq and the steps that can be applied to practical projects. You can download and run all the examples directly on the practice board (Zynq mini 7020), so it is also fun to study. If you understand all the contents of this lecture, you will acquire skills that can be applied to practical projects right away. I hope you will challenge the new world of Zynq.

#2.
Easy even for beginners
Gain practical knowledge.

It is helpful to organize the lecture content into an electronic document (PDF) to study multiple times. You can download and check all the lecture content on the practice board (Zynq mini 7020). The tool settings and usage are also explained in detail, so even beginners can easily follow along. The ultimate goal of the lecture is to develop the ability to apply it to practice. If you fully understand the lecture content, you can take charge of a project in practice and proceed.

Using Verilog
Using ZYNQ

This is the first lecture of “ Using ZYNQ with Verilog ” . All the contents of this lecture are designed to be practiced on the “Zynq mini 7020” board . If you purchase the lecture, you can download and use all the sources explained in the lecture from the data room . The source materials in the data room are composed of sources that were verified one by one by creating a project by chapter when this lecture was created .

ZYNQ is an FPGA released by Xilinx for Soc (System on Chip) . The FPGA contains an ARM Processor . Users can implement the Arm Core Processor and User Logic with a single chip . Embedded SW and User Logic can be configured with a single chip without having to use a separate external Processor .

The ultimate goal of this lecture is to acquire the technology to configure “Embedded_SW + User_Logic” when proceeding with a project utilizing ZYNQ . If you fully understand the contents of this lecture , you will be able to design and implement most projects utilizing ZYNQ . Rather than trying to understand the contents of this lecture just with your eyes , please create a project yourself according to the contents explained in the lecture, implement the code, download it to the board, and check the result . The world of FPGAs is not a world that can be learned by understanding with your eyes . You will learn little by little by directly programming, downloading it to the board, and checking the results through this process . For those who want to understand with their eyes, it is better to watch the video lecture .

 

Detailed Curriculum
  1. outline
  2. HW configuration
    1. Board configuration
    2. Bank structure
    3. MIO (Multiplexed IO)
    4. Circuit diagram
      1. Bank500
      2. Bank501
      3. Bank502
      4. Bank34
      5. Bank35
  3. SW Installation
  4. Basic Template Implementation
    1. Create a project
    2. Create Block Design
  5. Download the program
    1. Download in Debug Mode
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    2. Download using FSBL
      1. Create a project
      2. Add PL logic
      3. Bitstream Generation
      4. FSBL implementation
      5. Create Boot Image
      6. Download and check results
    3. Download using FSBL, Application SW
      1. Create a FSBL project
      2. Create an Application Project
      3. Create Boot Image
      4. Download and check results
  6. GPIO
    1. GPIOPS implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    2. Interrupt implementation
      1. Download and check results
    3. AXI GPIO implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    4. Implementing AXI GPIO Interrupts
      1. Create a project
      2. Application sw implementation
      3. Download and check results
  7. Timer
    1. Create a project
    2. Application sw implementation
    3. Download and check results
  8. Interrupt
    1. Create a project
    2. Application sw implementation
    3. Interrupts Analysis
    4. Download and check results
  9. PS-PL interface
    1. Block Memory Interface
      1. Create a project
      2. Add PL logic
      3. Application sw implementation
      4. Download and check results
    2. Implementing the PS-PL interface
      1. Create a project
      2. PL User Logic Implementation
      3. Application sw implementation
      4. Download and check results
    3. User Interface Implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
  10. Revision History

Q&A 💬

Q. Who is the target audience for this lecture?

This is for those who want to learn Xilinx Zynq. Even those who are new to Zynq can learn most of the contents of Zynq and apply them in practice by following the lecture.

Q. Is there anything I need to prepare to attend the lecture?

All content in the course uses materials verified on the Zynq mini 7020 board. You will need a Zynq mini 7020 board and Vitis 2022.1 tools before taking the course.

Q. What programming language do you use?

We use Verilog HDL, which is mainly used in enterprises.

Accumulated with 25 years of experience
We share our know-how on utilizing Verilog.

I have been working as a developer for over 20 years in large and small companies and currently run a small business. I have developed an ISP (Image Signal Processing) ASIC for CCTV and many products using FPGA such as OLED inspection equipment and DAQ (Data Acquisition System). In addition to FPGA, I have a lot of experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows Program.

💾 Please check the lecture environment.

  • The training board is Zynq mini 7020 (or 7010) . You can purchase it from Alina or other domestic shopping malls.
  • Windows OS environment, using Vivado 2022.1 .
  • This lecture is a text lecture in electronic document (PDF) format. (Approximately 80,000 characters/220 pages)

Recommended for
these people!

Who is this course right for?

  • Anyone interested in Verilog programming

  • Anyone interested in FPGA

  • Anyone interested in ZYNQ

Need to know before starting?

  • C language

  • Verilog language

Hello
This is ihil

Students

1,443

Reviews

50

Rating

4.8

Courses

17

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

  • Verilog HDL을 이용한 FPGA 설계

    • CCTV용 ISP ASIC 개발 (약 10년)

    • OLED Display 검사장비 개발 (약 3년)

    • FPGA를 이용한 장비 개발

  • MCU FW

    • STM32

    • PIC32

    • AVR, ATMEGA

    • DSP (TI)

  • Windows Application Program

    • Visual Studio MFC, C++

입니다.

Curriculum

All

219 lectures

Lecture resources

are provided.

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