Design Self-study Taste's Practical Verilog HDL Season 1 (From Clock to Internal Memory)

Learn about the provided practice files and execution environment. (Shared only with students)

[HDL Chapter 1] Generating a Clock in a Testbench (Don't discuss digital circuit design without a clock.)

[HDL Chapter 2] What are Testbench and DUT (Design Under Test)?

[HDL Chapter 3] Creating a Reset in Testbench (If there is no Reset, it will produce unintended results. It is an important signal!)

[HDL Chapter 4] Basic Logic for Storage! Understanding D FilpFlop (Don't make a Latch! You must make a Flip Flop.)

[HDL Chapter 5] D FlipFlop and Reset Practice (The importance of Reset can be said many times.)

[HDL Chapter 6] Understanding HW and Logic in Semiconductor Design (feat. Combinational Logic)

[HDL Chapter 7] Understanding Combinational Logic (Practice of 4-Axis Operations. 99.99% of the digital logic you design is Combinational + Sequential Logic.)

[HDL Chapter 8] Understanding Overflow and Setting Optimal Bits (Why does the value suddenly return to 0..?)

[HDL Chapter 9] Understanding Signed/Unsigned and Avoiding Operational Mistakes (I can't get the result I want..ㅠㅠ)

[HDL Chapter 10] Understanding Counters Properly to Improve Design Ability (Theory) - (If you understand counters properly, you will be better than a mediocre design beginner!)

[HDL Chapter 11] Understanding Counters Properly to Improve Design Capability (Practical Edition)

[HDL Chapter 12] Understanding Pipeline, the Secret of HW Accelerator (Basics) - (Parallel Processing is Basic, and One More Reason Why HW is Fast~!!)

[HDL Chapter 13] Let's understand the pipeline, the secret of HW accelerators (Theory)

[HDL Chapter 14] Let's understand the pipeline, the secret of HW accelerator (Practical)

[HDL Chapter 15] Let's understand FSM that controls the operation of HW. (Theory) - (If you understand the principle, you can design vending machines and clocks in no time.)

[HDL Chapter 16] Let's understand FSM that controls the operation of HW. (Practical)

[HDL Chapter 17] Let's understand FSM that controls the operation of HW. (Practical Application)

[HDL Chapter 18] Let's understand the types and characteristics of memory that non-memory design engineers should know.

[HDL Chapter 19] Let's understand the Internal Memory Interface (Understanding FPGA's BRAM - Theory)

[HDL Chapter 20] Let's understand the Internal Memory Interface (Understanding FPGA's BRAM - Practical)

What should I study next?

You are a "non-memory semiconductor design engineer." See you in the field.

[Chapter 1 of Break] What can you do if you learn non-memory design (Verilog HDL)?! (Looking at Samsung recruitment notice)

[Chapter 2 of Break] Who will be the winner of AI Inference Accelerator? Let's find out the current status of GPU, NPU, and FPGA

[Chapter 5 Break] Curriculum for Non-Memory Design?? Career Path?? Knowledge?? (There is no correct answer ^^)

[Chapter 7 Break] Don't Draw Timing Diagrams by Hand... (WaveDrom Tutorial)

[Chapter 8 Break] Verilog HDL Problem Bank!! Let's try HDLBits.

[Chapter 9 Break] Let's check the schematic of the Verilog HDL code!

[Verilog HDL/FPGA Extra 1 - Making a Clock] Matbi Watch Practice File (Shared only with students)

[Verilog HDL/FPGA Extra 1 - Making a Clock] Chapter 1. Making 1 Second

[Verilog HDL/FPGA Extra 1 - Making a Clock] Chapter 2. Making Hours, Minutes, and Seconds - Part 1

[Verilog HDL/FPGA Extra 1 - Making a Clock] Chapter 2. Making Hours, Minutes, and Seconds - Part 2

[Verilog HDL/FPGA Extra 1 - Making a Clock] Chapter 3. Let's upload it to FPGA and check it out!

[Verilog HDL/FPGA Extra 1 - Making a Clock] Chapter 4. Registering on Hackster.io (Manage your portfolio and share it with people around the world)