Design Self-Study Tastebi's Practical Verilog HDL Season 1 (From Clock to Internal Memory)

Let's explore the practice files and execution environment provided. (Shared only with students~)

[HDL Chapter 1] Generating Clocks in a Testbench (Don't discuss digital circuit design without clocks.)

[HDL Chapter 2] What are Testbenches and DUTs (Design Under Test)?

[HDL Chapter 3] Creating Reset in Testbench (Without a Reset, unintended results can occur. It's an important signal!)

[HDL Chapter 4] Basic Logic for Storage! Understanding D Flip-Flops (Don't Create Latches! You Must Create Flip-Flops.)

[HDL Chapter 5] D Flip-Flop and Reset Practice (The importance of Reset cannot be overstated.)

[HDL Chapter 6] Understanding HW and Logic in Semiconductor Design (feat. a little Combinational Logic...)

[HDL Chapter 7] Understanding Combinational Logic (Four Arithmetic Operations Practice. 99.99% of the digital logic you design is Combinational + Sequential Logic.)

[HDL Chapter 8] Understanding Overflow and Setting the Optimal Bit (Why does the value suddenly return to 0...?)

[HDL Chapter 9] Understanding Signed / Unsigned and Avoiding Calculation Mistakes (My desired result isn't coming out... 😭😭)

[HDL Chapter 10] Understanding Counters Properly to Improve Design Skills (Theory) - (Even just understanding counters properly makes you better than a mediocre new design employee!)

[HDL Chapter 11] Understanding Counters Properly to Improve Design Skills (Practical Exercises)

[HDL Chapter 12] Understanding Pipeline, the Secret of HW Accelerators (Basic) - (Parallel processing is fundamental, and one more reason why HW is fast~!!)

[HDL Chapter 13] Let's Understand Pipeline, the Secret of HW Accelerators (Theory)

[HDL Chapter 14] Let's Understand Pipeline, the Secret of HW Accelerators (Practical Exercise)

[HDL Chapter 15] Let's understand the FSM that controls the operation of HW (Theory) - (Once you understand the principle, you can quickly design vending machines and clocks.)

[HDL Chapter 16] Let's understand FSMs that control the operation of HW (Practical Exercise).

[HDL Chapter 17] Let's understand FSMs for controlling HW operation. (Practical Application)

[HDL Chapter 18] Let's understand the types and characteristics of memory that non-memory design engineers should know.

[HDL Chapter 19] Let's Understand Internal Memory Interface (Understanding FPGA's BRAM - Theory)

Let's understand the Internal Memory Interface (Understanding FPGA's BRAM - Practical Exercise)

What should I study next?

You are "non-memory semiconductor design engineers." See you in the field.

[Taking a Break Chapter 1] What can you do after learning Non-Memory Design (Verilog HDL)?! (Looking at Samsung Job Postings)

[Taking a Break - Chapter 2] Who Will Win the AI Inference Accelerator Race? Let's Explore the Current Status of GPUs, NPUs, and FPGAs

[Take a Break Chapter 5] Curriculum?? Career Path?? Knowledge?? for Non-Memory Design (There is no right answer ^^)

[Taking a Break, Chapter 7] Don't Draw Timing Diagrams by Hand... (WaveDrom Tutorial)

[Take a Break Chapter 8] Let's try HDLBits, a Verilog HDL question bank!!

[Take a Break Chapter 9] Let's Check the Schematic of a Verilog HDL Code!

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Matbi Watch practice files (Shared only with students~)

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Chapter 1. Making 1 Second

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Chapter 2. Making Hours, Minutes, and Seconds - Part 1

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Chapter 2. Making Hours, Minutes, and Seconds - Part 2

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Chapter 3. Let's Upload to the FPGA and Check!

[Verilog HDL/FPGA Side Story 1 - Making a Clock] Chapter 4. Registering on Hackster.io (Manage your portfolio and share with people around the world)