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인프런 영문 브랜드 로고
Hardware

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Embedded IoT

Verilog FPGA Program 1 (Zynq mini 7020)

In this course, students will learn how to implement Verilog using the Zynq board.

(5.0) 2 reviews

71 students

Verilog HDL
FPGA
zynq

This course is prepared for Basic Learners.

What you will learn!

  • Verilog coding

  • Utilizing ZYNQ Board

  • How to use Vivado, Vitis

  • Create a Test Bench and Verify Simulation

  • Download to board and check results

The core of implementing + practicing using the Zynq board.

📢 Please note before taking the class.

  • This lecture is a text lecture in the form of an electronic document (PDF). (Approximately 110,000 characters) All source files explained in the lecture are provided to those who take the lecture. The lecture source code can be downloaded from Section 0 [Material Sharing Link].

Verilog implementation using Zynq board

✅ Code implementation ✅ Simulation verification using Text Bench ✅ Board verification

Before coding, we analyze the entire system and provide know-how on how to code efficiently. We explain in an easy-to-understand manner based on many techniques and know-how experienced in the field for the past 20 years. Also, the source codes included in the lecture are not codes for study, but codes used in practice. All those who attend the lecture will be provided with the entire source code used in the lecture.

The first half of the lecture will cover the following two topics:

  • Install Vivado 2022.1
  • Download the code implemented on the Zynq board and check the results

In the latter part of the lecture, we will verify the results downloaded to the board through coding and simulation verification for each topic.

  • LED control using counter
  • SPI Contoller Implementation
  • UART Controller Implementation
  • I2C Contoller Implementation
  • Uses Xilinx IP (Clock Generator, Memory Generator)
  • NRZL Decoder Implementation
  • Implementation of FMC (Flexible Memory Controller) Interface

FPGA Utilization with Verilog for ZYNQ - Lecture Preview

Detailed Curriculum
  1. outline
  2. HW configuration
  3. SW Installation
  4. Download ZynQ Board
    1. Basic Template Configuration
      1. Create a project
      2. Create Block Design
    2. Download in Debug Mode
      1. Add source code
      2. Bitstream Generation
      3. Run and download Vitis
    3. Download using FSBL (First Stage Bootloader)
      1. Create a FSBL project
      2. Create Boot Image
      3. Download the board and check the results
    4. Download using FSBL, Application SW
      1. Create a FSBL project
      2. Create an Application Project
      3. Create Boot Image
    5. Download the board and check the results
      1. LED control using counter
      2. Create a project
      3. Project screen configuration
      4. Add source code
      5. Text Editor Settings
      6. Code implementation
      7. XDC implementation
      8. Generate Bitstream
      9. Check the results
    6. Simulation
      1. Add simulation source file
      2. Implementing the tb_led_counter.v code
      3. Simulation in progress
      4. Simulation Results
    7. About the code
      1. Implementable code, non-implementable code
      2. The basic unit of code is Clock.
      3. All code is processed in parallel.
      4. ternary operator
      5. Use Register
      6. FSM (Finite State Machine)
    8. Spi Master Implementation
      1. Specs
      2. Code implementation
        1. Port Definition
        2. State Definition
        3. Code implementation
        4. Timing Diagram
      3. Simulation
        1. Test bench implementation
        2. Check simulation results
    9. Spi Slave Implementation
      1. Specs
      2. Code implementation
        1. Port Definition
        2. State Definition
        3. Code implementation
      3. Simulation
        1. Test bench implementation
        2. Check simulation results
    10. Implementing Spi Communication
      1. Remove button noise
        1. Button circuit
        2. Code implementation
        3. Simulation
      2. SPI Task Implementation
        1. Port Definition
        2. Remove button noise
        3. State Definition
        4. Code implementation
      3. Simulation
        1. Test bench implementation
        2. Check simulation results
      4. Implementing UsetTop module
      5. Add xdc file
      6. Generate Bitstream
      7. Download the board and check the results
    11. Using Xilinx IP
      1. Create a Clock
      2. Memory Creation
        1. Block Memory Generator
      3. Memory Test
        1. Single Port RAM
        2. Simple Dual Port RAM
        3. Other memory
    12. UART Controller Implementation
      1. Uart Tx implementation
        1. Code implementation
        2. simulation
      2. Uart Rx implementation
        1. Create FIFO
        2. Code implementation
        3. simulation
      3. Uart Controller Implementation
      4. LoopBack implementation
        1. composition
        2. Code implementation
        3. simulation
        4. Implementing the UserTop module
        5. xdc generation
        6. Generate Bitstream, XSA files
        7. Check the results
    13. I2C Controller Implementation
      1. I2C Controller Specification
        1. Start, Stop Condition
        2. 8bits data transfer
        3. Slave ID
        4. I2C Write Data Structure
        5. I2C Read Data Structure
      2. I2C Master Implementation
        1. i2c_master write signal analysis
        2. i2c_master read signal analysis
        3. Implementing i2c_master code
        4. i2c_master simulation
        5. Check the results
        6. i2c_master8x8 implementation
        7. i2c_master8x8 simulation
      3. I2C Slave Implementation
        1. I2C Slave Signal Analysis
        2. i2c_slave8x8 code implementation
        3. i2c_reg8x8 implementation
        4. i2c_slave8x8, i2c_reg8x8 simulation
      4. I2C TASK
        1. Implementing i2c_task code
      5. Implementing the UserTop module
      6. Add xdc file
      7. Generate Bitstream, XSA files
      8. Download the board and check the results
    14. NRZL Decoder Implementation
      1. System Overview
      2. Code implementation
        1. Create clock
        2. Create FIFO
        3. data_counter implementation
        4. noise_reduction implementation
        5. data_encoder implementation
        6. nrzlDecTop implementation
        7. Implementing the UserTop module
        8. xdc implementation
        9. Create Bitstream, XSA files, and check results
        10. conclusion
    15. FMC Interface Implementation
      1. FMC Timing
      2. Code implementation
        1. fmc_model.v
        2. simulation fmc_model
        3. fmc_interface.v
        4. sys_host.v
        5. spram_32x8192
        6. simulation fmc_interface
        7. fmc_top.v
        8. UserTop.v
        9. UserTop.xdc
      3. Bitstream Generation
      4. Troubleshooting Timing Errors
      5. Download the board and check the results
      6. conclusion
    16. Revision History

Q&A 💬

Q. Who is the target audience for this lecture?

This course is for those who want to learn Verilog and FPGA. This course has reorganized the content so that "FPGA Utilization with Verilog" can be implemented on the Zynq board, and all source codes use materials verified on the Zynq mini 7020 (7010) board.

Q. Is there anything I need to prepare to attend the lecture?

All the contents of the lecture can be practiced on the Zynq mini 7020 (7010) board. If you prepare the Zynq mini 7020 (7010) board, it will be very helpful because you can implement the code yourself and check the results.

Q. What program tools do you use?

I am using Vivado 2022.1 version. There is a section in the lecture about installing tools, so please install them according to the lecture.

Q. Where can I buy the Zynq mini board?

You can purchase it through domestic shopping malls or AliExpress.

Accumulated with 25 years of experience
We share our know-how on utilizing Verilog.

I have been working as a developer for over 20 years in large and small companies and currently run a small business. I have developed an ISP (Image Signal Processing) ASIC for CCTV and many products using FPGA such as OLED inspection equipment and DAQ (Data Acquisition System). In addition to FPGA, I have a lot of experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows Program.

💾 Please check the lecture environment.

  • For the practice environment, we use Windows OS, Vivado 2022.1.
  • This lecture is a text lecture in electronic document (PDF) format. (Approximately 110,000 characters)

Recommended for
these people!

Who is this course right for?

  • For those who want to learn FPGA

  • For those who want to learn Verilog

  • For those who want to learn Zynq

Need to know before starting?

  • C language

  • Verilog Language (Basics)

Hello
This is ihil

Students

1,443

Reviews

50

Rating

4.8

Courses

17

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

  • Verilog HDL을 이용한 FPGA 설계

    • CCTV용 ISP ASIC 개발 (약 10년)

    • OLED Display 검사장비 개발 (약 3년)

    • FPGA를 이용한 장비 개발

  • MCU FW

    • STM32

    • PIC32

    • AVR, ATMEGA

    • DSP (TI)

  • Windows Application Program

    • Visual Studio MFC, C++

입니다.

Curriculum

All

381 lectures

Lecture resources

are provided.

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