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Semiconductor

Verilog FPGA Program 1 (Arty A7-35T)

FPGA implementation using Verilog

(5.0) 14 reviews

178 students

Verilog HDL
FPGA

This course is prepared for Basic Learners.

What you will learn!

  • Verilog RTL Design

  • FPGA Design

Are you interested in FPGAs?
Then do Verilog! 😁

Verilog?

Verilog, which has a similar grammar to the C language, is a hardware description language (HDL) used for electronic circuits and systems. It is used for various purposes such as circuit design, verification, and implementation.

FPGA Design by someone with over 20 years of experience 📑

There are many developers who are interested in implementing FPGAs using Verilog. However, it is very difficult to find a lecture that explains this in detail. Now, meet a lecture that summarizes the contents used in development by a current professional for more than 20 years! The lecture content may seem difficult, but if you read it carefully 3-4 times and practice it, it will be a good guide for you to grow as an FPGA developer.

This lecture covers in detail the implementation of FPGA using Verilog HDL. You will learn the entire process of implementing Verilog code , verifying the results through simulation , and finally downloading the implemented content to the Arty A7 board and verifying the results . In addition, IP (clock-related, memory-related) provided by Xilinx is covered. If you understand the content explained in this lecture and learn your own coding method, you will become a skilled developer in FPGA design.

📢 Please make sure to check before taking the class!

  • This lecture is a text lecture in electronic document format . All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.
  • The tool used is vivado 2018.3, and the board used for practice is Arty A7-35T (100T).
  • Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.

Learn things like this 📚

How to use vivado tools

Verilog coding

Create a tech bench
 Doing a simulation

Results on the board
Download and check

A word from a knowledge sharer 🙋‍♀️

I have been developing using FPGA for about 20 years. I have also made and released ASIC. However, I still do not fully understand the world of FPGA. The world of FPGA is that wide. You need to know a lot about tools, HW, Verilog, etc. What I have felt while working so far is that in order to handle Verilog or FPGA well, you need to have your own program format (coding rules) . This lecture explains this part in detail. I hope you learn the content explained in the lecture and create your own format.

This lecture is for those who have some knowledge of Verilog grammar and understand HW contents . Since Verilog HDL is similar to C language, it will be helpful to know C language. Also, this lecture downloads the final result to the board (Arty A7, Digilent) and checks the result. Verilog HDL should not end with checking the result in Simulation. Verilog HDL must be downloaded to the FPGA board and the operation must be confirmed. Those who take this lecture are recommended to first look at the content and purchase a practice board to check the result.

If there is anything you do not understand in the lecture, please post a question through the Inflearn community or the cafe I run and I will answer it.

Lecture Features ✨

The structure of this lecture is as follows.

  • Code implementation
  • Simulation verification using test bench
  • Board Verification

We will explain in detail how each process is carried out through the vivado 2018.3 version.

The practical content is as follows.

  1. LED on/off using counter
  2. SPI Master Implementation
  3. SPI Slave Implementation
  4. SPI Master/Slave communication implementation and board verification
  5. Xilinx IP-1 (Clock Generator)
  6. Xilinx IP - 2 (Memory Generator)
  7. UART Controller Implementation
  8. I2C Controller Implementation
  9. NRZL Decoder Implementation
  10. FMC Interface Implementation
  11. Block Memory Speed

The first practical content is counter. Counter is a simple module, but it is actually used a lot. Design a counter, create a test bench, and simulate whether the implemented code works properly. Finally, apply it to the board and check the result by turning the LED on/off.

The second practical topic is SPI communication. The reason why SPI was chosen is because it is an interface that is relatively easy to implement among various interfaces and is actually widely used. First, implement SPI Master, and then implement SPI Slave. Then, implement communication between Master and Slave and check if it works properly on the board.

The third content explains Clock and Memory, which are widely used and easily accessible IPs provided by Xilinx.

The fourth content is UART communication. We will implement a Uart Controller and verify it through communication with a PC.

The fifth practical topic is I2C communication. I2C communication looks simple, but implementing it in code is not easy at all. It is 2~3 times more difficult than SPI. If you implement I2C Master and Slave in code, you can implement other interfaces without difficulty. Before implementing the code, we will cover in detail how to set the specifications and how to design the SM (State Machine). The implemented I2C Controller will be verified to operate on the board.

The sixth content is a new addition to v2.1. It implements a Non-Return Zero Level (NRZL) Decoder. In particular, it explains in detail how to design and use FIFO. FIFO is a very important IP used in many fields. Through this chapter, you can understand how to design and implement FIFO.

The seventh content is what was added in v2.3. It implements the FMC(Flexible Memory Controller) Interface. In particular, it includes how to solve Timing Violations that commonly occur when using more than two clocks.

The eighth content is what was added in v2.4. It tests the speed (performance) of the Block Memory inside the FPGA and determines what the most appropriate speed is.

Are you curious about the detailed curriculum?
  1. outline
  2. HW configuration
    1. Method using USB-JTAG
    2. Method using JTAG-HS3
  3. LED control using counter
    1. Function definition
    2. Create a project
    3. Project screen configuration
    4. Add source code
    5. Text Editor Settings
    6. Code implementation
    7. XDC implementation
    8. Generate Bitstream
    9. Download Bitstream
    10. Check the results
  4. Simulation
    1. Add simulation source file
    2. Implementing the tb_led_counter.v code
    3. Simulation in progress
    4. Simulation Results
  5. Spi Master Implementation
    1. Specs
    2. Create a project
    3. Add source code
    4. Code implementation
      1. Port Definition
      2. State Definition
      3. Code implementation
      4. Timing Diagram
    5. Simulation
      1. Test bench implementation
      2. Check simulation results
  6. Spi Slave Implementation
    1. Specs
    2. Add source code
    3. Code implementation
      1. Port Definition
      2. State Definition
      3. Code implementation
    4. Simulation
      1. Test bench implementation
      2. Check simulation results
  7. Implementing Spi Communication
    1. Remove button noise
      1. Button circuit
      2. Code implementation
      3. Simulation
    2. SPI Task Implementation
      1. Port Definition
      2. Remove button noise
      3. State Definition
      4. Code implementation
    3. Simulation
      1. Test bench implementation
      2. Check simulation results
    4. Bitstream generation and download
  8. Using Xilinx IP
    1. Create a Clock
    2. Clock IP Test
      1. Specs
      2. Code implementation
      3. xdc file
      4. Bitstream generation and download
    3. Memory Creation
      1. Block Memory Generator
    4. Memory Test
      1. Single Port RAM
      2. Simple Dual Port RAM
      3. Other memory
  9. UART Controller Implementation
    1. Uart Tx implementation
      1. Code implementation
      2. Simulation
    2. Uart Rx implementation
      1. Create FIFO
      2. Code implementation
      3. Simulation
    3. Uart Controller Implementation
    4. LoopBack implementation
      1. composition
      2. Code implementation
      3. Simulation
      4. Bitstream Generation
      5. Check the results
  10. I2C Controller Implementation
    1. I2C Controller Specification
      1. Start, Stop Condition
      2. 8bits data transfer
      3. Slave ID
      4. I2C Write Data Structure
      5. I2C Read Data Structure
    2. I2C Master Implementation
      1. i2c_master write signal analysis
      2. i2c_master read signal analysis
      3. Implementing i2c_master code
      4. i2c_master simulation
      5. Check the results
      6. i2c_master8x8 implementation
      7. i2c_master8x8 simulation
    3. I2C Slave Implementation
      1. I2C Slave Signal Analysis
      2. i2c_slave8x8 code implementation
      3. i2c_reg8x8 implementation
      4. i2c_slave8x8, i2c_reg8x8 simulation
    4. I2C TASK
      1. Implementing i2c_task code
      2. Check the results
  11. NRZL Decoder Implementation
    1. System Overview
    2. Code implementation
      1. Create a project
      2. Code implementation
      3. data_counter implementation
      4. noise_reduction implementation
      5. data_encoder implementation
      6. nrzlDecTop implementation
      7. xdc implementation
      8. Generate Bitstream & Download, Verify
      9. conclusion
  12. FMC Interface Implementation
    1. FMC Timing
    2. Code implementation
      1. Create a project
      2. fmc_model.v
      3. simulation fmc_model
      4. fmc_interface.v
      5. sys_host.v
      6. spram_32x8192
      7. simulation fmc_interface
      8. fmc_top.v
      9. fmc_top.xdc
    3. Bitstream Generation
    4. Troubleshooting Timing Errors
    5. Download the board and check the results
    6. Download the board and check the results
  13. Block Memory Speed
    1. Action Scenario
    2. Block RAM implementation
    3. Code implementation
    4. Simulation
    5. xdc file
    6. File Structure
    7. Check the results
    8. conclusion
  14. Revision History

Expected Questions Q&A 💬

Q. Who is the target audience for this lecture?

You should have some (beginner) knowledge of Verilog grammar and basic knowledge of HW.

Q. Is there anything I need to prepare to attend the lecture?

The lecture will be conducted on a practice board (Arty A7 -35T or 100T, Digilent product). However, if you do not have a board, you can listen to the lecture first, proceed as explained in the lecture (coding and simulation), and then proceed with the practice later when the board is ready. In addition, JTAG-HS2 (or HS3) is used to download to the board.

Q. What program tools do you use?

This lecture is for Xilinx FPGA. The SW tool uses vivado 2018.3 version. The SW installation is not included. Please install the SW tool (vivado 2018.3 or later) before taking the lecture.

Introducing the knowledge sharer ✒️

I have been working as a developer for over 20 years in large and small companies and currently run a small business. I have developed an ISP (Image Signal Processing) ASIC for CCTV and many products using FPGA such as OLED inspection equipment and DAQ (Data Acquisition System). In addition to FPGA, I have a lot of experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows Program.

Recommended for
these people!

Who is this course right for?

  • If you are interested in FPGA

  • Anyone interested in Verilog

  • If you want to upgrade your Verilog skills

  • If you want to upgrade your FPGA

Need to know before starting?

  • Verilog HDL

  • FPGA

Hello
This is ihil

Students

1,443

Reviews

50

Rating

4.8

Courses

17

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

  • Verilog HDL을 이용한 FPGA 설계

    • CCTV용 ISP ASIC 개발 (약 10년)

    • OLED Display 검사장비 개발 (약 3년)

    • FPGA를 이용한 장비 개발

  • MCU FW

    • STM32

    • PIC32

    • AVR, ATMEGA

    • DSP (TI)

  • Windows Application Program

    • Visual Studio MFC, C++

입니다.

Curriculum

All

332 lectures

Lecture resources

are provided.

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