Item: Design Self-study Taste's Practical Verilog HDL Season 2 (AMBA AXI4 Complete Conquest)
Rating: 5
Author: whdgns35855485

I interned in a SoC-related department during my undergraduate years, and I remember starting without knowing anything about AMBA Specs, so I put in a lot of effort and time... I wish I had taken this lecture back then, I could have learned so much more, it's a shame 😊.. It was a really great lecture! Thank you :)


whdgns35855485

Let's gain experience in AMBA AXI4 design and VIP verification, which are the basis of SoC Bus, using Verilog HDL along with self-study design!

semisgdh

상반기 깜짝 30% 할인

Design Self-study Taste's Practical Verilog HDL Season 2 (AMBA AXI4 Complete Conquest)

Thank you so much for your valuable experience and heartfelt review.
It would be rewarding if our lecture could fill the void you felt back then, even just a little 🙏
We will continue to improve in the future to provide more informative lectures that are directly applicable to practical work.
Happy studying!!


설계독학과 함께 Verilog HDL을 이용하여 SoC Bus의 기본이 되는 AMBA AXI4 설계와 VIP 검증 경험을 쌓아봅시다!

설계독학맛비

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

amba

Embedded

임베디드

설계독학맛비's 실전 Verilog HDL Season 2 (AMBA AXI4 완전정복)

설계독학맛비's Verilog HDL Season2 를 시작하기 전에

Data 전송의 기본이되는 Valid / Ready Handshake 설계 정복하기

원활한 Data 전송을 위한 필수 Buffer, FIFO 설계 정복하기

AXI4 Interface 를 설계하기 위한 이론 및 검증환경 숙지하기

AXI4-Lite 설계 정복하기

AXI4-Stream 설계 정복하기

AXI4 설계 정복하기 (feat. 설계엔지니어라면 꼭 알고 있어야하는 내용들!!)

Mem copy IP. DMA (Direct Memory Access) 설계하기.

[프로젝트] "Matbi Mem copy IP" 를 FPGA 에 올려보자! (동작 및 Performance 확인)

마치며