인프런 커뮤니티 질문&답변

기존에 이미 작성되어있던 코드를 지우고 제가 영상보면서 연습 차 다시 작성했는데..-_-;

저장하고 그 후에 ./build 실행하니 다양한 오류가 뜨더라구요...

raineesm@DESKTOP-VLU7A79:~/Matbi_VerilogHDL_Season1/chapter_2$ ./build

WARNING: [XSIM 43-3479] Unable to increase the current process stack size.

INFO: [VRFC 10-2263] Analyzing Verilog file "/home/raineesm/Matbi_VerilogHDL_Season1/chapter_2/tb_clock_generator.v" into library work

INFO: [VRFC 10-311] analyzing module tb_clock_generator

ERROR: [VRFC 10-8414] extra comma in port association list is not allowed [/home/raineesm/Matbi_VerilogHDL_Season1/chapter_2/tb_clock_generator.v:56]

ERROR: [VRFC 10-8530] module 'tb_clock_generator' is ignored due to previous errors [/home/raineesm/Matbi_VerilogHDL_Season1/chapter_2/tb_clock_generator.v:21]

Vivado Simulator v2022.2

Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.

Running: /home/raineesm/tools/Xilinx/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab tb_clock_generator -debug wave -s tb_clock_generator

Multi-threading is on. Using 2 slave threads.

ERROR: [XSIM 43-3225] Cannot find design unit work.tb_clock_generator in library work located at xsim.dir/work.

ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/tb_clock_generator/xsimk" does not exist