작성
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안녕하세요. 그동안 바뻐서 못듣다가 다시 듣기시작했는데
저번까지 잘되던 빌드가 다시 와서 하려고하니까 안되네용
kkm32160126@DESKTOP-NT884HJ:~/Matbi_VerilogHDL_Season1/chapter_2$ source /mnt/d/vivado/vivado/2020.2/settings64.sh
kkm32160126@DESKTOP-NT884HJ:~/Matbi_VerilogHDL_Season1/chapter_2$ ./build
WARNING: [XSIM 43-3479] Unable to increase the current process stack size.
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/kkm32160126/Matbi_VerilogHDL_Season1/chapter_2/tb_clock_generator.v" into library work
INFO: [VRFC 10-311] analyzing module tb_clock_generator
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/kkm32160126/Matbi_VerilogHDL_Season1/chapter_2/clock_gating_model.v" into library work
INFO: [VRFC 10-311] analyzing module clock_gating_model
ERROR: [VRFC 10-4982] syntax error near '{' [/home/kkm32160126/Matbi_VerilogHDL_Season1/chapter_2/clock_gating_model.v:21]
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /mnt/d/vivado/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab tb_clock_generator -debug wave -s tb_clock_generator
Multi-threading is on. Using 2 slave threads.
ERROR: [XSIM 43-3225] Cannot find design unit work.tb_clock_generator in library work located at xsim.dir/work.
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/tb_clock_generator/xsimk" does not exist
답변 1
0
안녕하세요 :)
syntax error 같은데 코드 확인 부탁드려요.
찾기 어려우시면, 제공해드린 코드와 비교해보세요. :)
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